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VHF/UHF Tuner IC for Multi-Standard Digital TV
Preliminary Technical Data
FEATURES
Single-chip RF tuner IC for Multi-Standard Digital TV Applications in VHF and UHF VHF (54 MHz to 245 MHz) UHF (470 MHz to 862 MHz) Zero-IF architecture Low noise figure 3.5 dB Typical AGC dynamic range: -102 dBm to +10 dBm Low power consumption in continuous mode VHF: 98 mW UHF: 98 mW On-chip features include Fast switching fractional-N PLL Low phase noise and wide frequency range VCO PLL loop filter Bandwidth-adjustable low-pass filter Reference clock output for demodulators Integrated baseband PGA for direct connection to digital demodulators Noise/linearity optimization through internal RFAGC loop Adjustable take-over point I2C serial bus interface Small 24-lead lead frame chip scale package (LFCSP) (4 mm x 4 mm) Minimal external components 6 ea for UHF only 9 ea for dual-band
ADMTV803
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
CMMB (UHF band) /DTMB/ DVB-H/ DVB-T/ DAB/ T-DMB/ ATSC-M/H/ ISDB-T (full-seg, 3-seg and 1-seg) mobile and portable TV receivers VHF/UHF mobile and portable TV receivers
GENERAL DESCRIPTION
The ADMTV803 is a highly integrated CMOS zero-IF conversion tuner IC for multi-standard digital TV such as CMMB (UHF band), DTMB, DVB-H, DVB-T, DAB, T-DMB, ATSC-M/H and ISDB-T (full-seg, 3-seg and 1-seg). It supports dual RF input bands, VHF and UHF. The building blocks include LNA, RFPGA, I/Q down- conversion mixer, bandwidth adjustable low-pass filter, baseband PGA, and fractional-N frequency synthesizer with fully integrated VCO and PLL loop filter. The on-chip low phase noise VCO, along with the high resolution fractional-N frequency synthesizer makes in-band phase noise low enough for mobile TV applications.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The ADMTV803 consumes less than 9.8 mW for DVB-H mode at 10 % duty cycle. By using very small package size (LFCSP), the ADMTV803 is the best solution for mobile TV application especially for mobile phones, notebook PCs, PDAs, etc. where low power consumption is required critically. Applications for the ADMTV803 include CMMB (UHF band), DTMB, DVB-H, DVB-T, DAB, T-DMB, ATSC-M/H and ISDBT (full-seg, 3-seg and 1-seg).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADMTV803 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Electrical Characteristics...................................................... 3 Power and Digital Timing Characteristics................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 Low Noise Amplifier (LNA) ..................................................... 14 RF Programmable Gain Amplifier (PGA) .............................. 14 I/Q Downconverter.................................................................... 14 Local Oscillator........................................................................... 14 Baseband Programmable gain low-Pass Filter (LPF) and AGC ....................................................................................................... 15 Automatic Gain Control (AGC)............................................... 15 RF power detector and adjacent Received Signal Strength Indicator (ADJRSSI) .................................................................... 15
2
Preliminary Technical Data
I2C Interface and Clock Control............................................... 15 Power-Down Modes .................................................................. 15 Applications Information .............................................................. 16 Antenna application information ............................................ 17 RF Input Stage............................................................................. 18 VCO Bias/Bypass Capacitors.................................................... 18 Digital Interface-- SDA/SCL.................................................... 18 BBAGC Interconnections.......................................................... 18 XIN/Xout Interconnections ...................................................... 19 Reference Clock Selection......................................................... 19 PLL Setting .................................................................................. 19 RFAGC SETTING...................................................................... 20 BB Gain Setting .......................................................................... 20 Tspd control signal inverting .................................................... 21 Power-Down Control ................................................................ 21 I C Operation.................................................................................. 22 I2C Read/Write Address ............................................................ 22 I2C Bus Format............................................................................ 22 I2C Timing Characteristics........................................................ 22 I2C register MAP ........................................................................ 24 Register descriptions.................................................................. 25 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
03/09/2009--Revision PrB: Preliminary
Rev. PrB | Page 2 of 31
Preliminary Technical Data SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS
Table 1.
Parameter OPERATING CONDITIONS 1.8 V Supply Voltage (VDD18RF, VDD18VCO, LNALOAD, VDD18BB, VDD18DIG) I/O Supply Voltage (VDDIO) BBAGC Input Voltage BBAGC Input Current DIGITAL INPUT/OUTPUT PINS (TSPD, AS, SCL, SDA, CLKOUT) Maximum Low Input Voltage Minimum High Input Voltage Maximum Low Output Voltage Minimum High Output Voltage High Level Input Current (VIN = VDDIO) Low Level Input Current (VIN = GND) VHF POWER CONSUMPTION 1.8 V Analog Current Consumption 1.8 V Digital Current Consumption I/O Digital Current Consumption Power-Down Current Consumption Total Power Consumption UHF POWER CONSUMPTION 1.8 V Analog Current Consumption 1.8 V Digital Current Consumption I/O Digital Current Consumption Power-Down Current Consumption Total Power Consumption Symbol VDD18 VDDIO VBBAGC IBBAGC VIL VIH VOL VOH IIH IIL IDD18AVHF IDD18DVHF IDDIOVHF IPDVHF PVHF IDD18AUHF IDD18DUHF IDDIOUHF IPDUHF PUHF Min 1.7 1.7 0 -10 Typ 1.8 2.8
ADMTV803
Max 1.9 3.6 3.6 10 0.3 x VDDIO
Unit V V V A V V V V A A mA mA A A mW mA mA A A mW
0.7 x VDDIO 0.4 x VDDIO VDDIO - 0.4 -10 -10 50 4.5 3 TBD 98 50 4.5 3 TBD 98 10 10
Rev.PrB | Page 3 of 31
ADMTV803
AC ELECTRICAL CHARACTERISTICS
TA = 25C, VDD12 = 1.2 V, VDDIO = 2.8 V, unless otherwise noted. Table 2.
Parameter REFERENCE CRYSTAL OR CLOCK INPUT FREQUENCY VHF CHARACTERISTICS RF Frequency Range RF Input Impedance Input VSWR Typical AGC Dynamic Range Noise Figure @ Maximum Gain In-Band Two-Tone IMD3 (U/D) 1 Out-of-Band IIP3 2 3 dB Cutoff Frequency 3 Stop Band Attenuation 4 LO Phase Noise (SSB @ 100 kHz Offset) Baseband Output Amplitude Vpp, Single Baseband Output Pins (QP, QN, IN, IP) Minimum Load Resistance, Differential Maximum Load Capacitance, Differential Output DC Voltage UHF CHARACTERISTICS RF Frequency Range RF Input Impedance Input VSWR Typical AGC Dynamic Range Noise Figure @ Maximum Gain In-Band Two-Tone IMD3 (U/D)1 Out-of-Band IIP32 3 dB Cutoff Frequency3 Stop Band Attenuation4 LO Phase Noise (SSB @ 100 kHz Offset) Baseband Output Amplitude Vpp, Single BB Output Pins (QP, QN, IN, IP) Minimum Load Resistance, Differential Maximum Load Capacitance, Differential Output DC Voltage
1 2
Preliminary Technical Data
Symbol fCLK fVHF ZIN VSWR PIN NF IMD3IN IIP3OUT f3dB SBA PN100k VOUTAC RL MIN CL MAX VOUTDC fUHF ZIN VSWR PIN NF IMD3IN IIP3OUT f3dB SBA PN100k VOUTAC RL MIN CL MAX VOUTDC
Min 13 54
Typ
Max 40 245
Unit MHz MHz dBm dB dBc dBm MHz dBc dBc/Hz mV k pF V MHz dBm dB dBc dBm MHz dBc dBc/Hz mV k pF V
50 2:1 -102 3.5 70 -7 0.29 -65 -107 500 2
3:1 10
4
700
20 0.9 470 50 2:1 -102 3.5 63 -8 0.29 -65 -97 500 2 20 0.9 4 862 3:1 10
700
For RF input power, PIN < -30dBm, f1-f2=500kHz frequency offset
For RF input power, PIN = -80dBm, two-tone interferer power = -35dBm, f1 = 13.25 MHz frequency offset, f2 = 29.25 MHz frequency offset. RFAGC: closed-loop gain control, BBAGC: external gain control.
3
Programmable MULTI-BAND CHARACTERISTICS Signal Bandwidth (MHz) 3 dB Cutoff Frequency (MHz) CMMB 2, 8 1, 4 DTMB, DVB-H, DVB-T 5, 6, 7, 8 2.5, 3, 3.5, 4 DAB, T-DMB 1.536 0.768 ATSC-M/H 6 3 ISDB-T full-seg 6 3 ISDB-T 3-seg 1.29 0.645 ISDB-T1-seg 0.43 0.29
4
For 4.87 MHz offset @ 4MHz LPF offset
Rev. PrB | Page 4 of 31
Preliminary Technical Data
POWER AND DIGITAL TIMING CHARACTERISTICS
Table 3.
Parameter TSPD Setup Margin Power-Up Setup Margin for VDD18 Power-Up Setup Margin for VDDIO Setup Time for I2C Interface
1
ADMTV803
Symbol1 A B C D
Min Don't Care Don't Care Don't Care 10
Unit s s s s
see figure 2.
Figure 2 . Power and Digital Timing Diagram
Rev.PrB | Page 5 of 31
ADMTV803 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter 1.8 V Supply Voltage (VDD18) I/O Supply Voltage (VDDIO) Analog Input Voltage Digital Input Voltage Analog Output Voltage Digital Output Voltage Operating Temperature Range Storage Temperature Range Rating -0.5 V to +2.1 V -0.5 V to + 4.0 V -0.5 V to VDD18 + 0.3 V -0.5 V to VDDIO + 0.5 V -0.5 V to VDD18 + 0.3 V -0.5 V to VDDIO + 0.5 V -40C to +85C -65C to +150C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ESD CAUTION
Rev. PrB | Page 6 of 31
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
URFIN VDD18BB RSSI
ADMTV803
IN XTALO
IP
Figure 3. Pin Configuration [LFCSP]
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic VRFIN VS LNALOAD VDD18RF REGCAP VDD18VCO AS I/O Type1 AI AO P P P P DI Description VHF RF Input. VHF LNA Source. A 3.3 nH inductor should be connected as close as possible between this pin and GND. RF Power (1.8 V). This pin should be decoupled with a 1 nF capacitor. RF Power (1.8 V). This pin should be decoupled with a 1 nF capacitor. Regulator output decoupling capacitor. This pin should be decoupled with a 470 nF capacitor. VCO Power (1.8 V). This pin should be decoupled with a 1 nF capacitor. Address Selection. The I2C address can be determined by the AS pin. If AS is connected to GND, read mode address = 0xC3, write mode address = 0xC2. If AS is connected to VDDIO, read mode address = 0xC5, write mode address = 0xC4. Time-Slicing Power-Down. Apply 0 V to this pin for normal operation. Apply VDDIO for time-slicing power-down. I2C Data. Bidirectional pin. 10k pull up resistor is embedded on chip. I2C Clock. 10k pull up resistor is embedded on chip. Crystal Oscillator Output. Crystal Oscillator Input. Clock Output. Digital Power (1.8 V). Wide Range I/O Power (1.8 V to 3.3 V). BBAGC Input (0 V to 3.3 V). No connection. Quadrature-Phase Positive Output. Quadrature-Phase Negative Output. In-Phase Negative Output. In-Phase Positive Output. RSSI Output voltage for Adjacent Channels. A 33nF capacitor should be connected as close as possible between this pin and GND. Baseband Block Power (1.8 V). This pin should be decoupled with a 100 nF capacitor. UHF RF Input.
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
TSPD SDA SCL XTALO XTALI CLKOUT VDD18DIG VDDIO BBAGC NC QP QN IN IP RSSI VDD18BB URFIN
DI DB DI AO AI AO P P AI AO AO AO AO AO P AI
AI = Analog input, AO = Analog output, DI = Digital input, DO = Digital output, DB = Digital bidirectional, P = Power
Rev. PrB | Page 7 of 31
XTALI
AS
TSPD
SDA
SCL
QN
ADMTV803 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VDD18 = 1.8 V, VDDIO = 3.3 V, unless otherwise noted.
Preliminary Technical Data
Figure 4. UHF Receiver Mode Current vs. Supply Voltage
Figure 7. UHF Noise Figure vs. Input Power
Figure 5. UHF Maximum Voltage Gain vs. Frequency
Figure 8. UHF Input Return Loss (S11) vs. Frequency (High LNA Gain Mode)
Figure 6. UHF Noise Figure vs. Frequency
Figure 9. UHF Input Return Loss (S11) vs. Frequency (Very Low LNA Gain Mode)
Rev. PrB | Page 8 of 31
Preliminary Technical Data
ADMTV803
Figure 10. UHF In-Band IIP3 vs. Input Power
Figure 13. UHF Power-Down Mode Current vs. Supply Voltage
Figure 11. UHF In-Band IMD3 vs. Frequency
Figure 14. UHF Phase Noise vs. Offset Frequency
Figure 12. UHF Out-of-Band IIP3 vs. Frequency
Figure 15. Port-to-Port Isolation
Rev. PrB | Page 9 of 31
ADMTV803
Preliminary Technical Data
Figure 16. UHF Tunable Low-Pass Filter Response
Figure 19. VHF Maximum Voltage Gain vs. Frequency
Figure 17. UHF Tunable Low-Pass Filter Attenuation
Figure 20. VHF Noise Figure vs. Frequency
Figure 18. VHF Receiver Mode Current vs. Supply Voltage
Figure 21. VHF Noise Figure vs. Input Power
Rev. PrB | Page 10 of 31
Preliminary Technical Data
ADMTV803
Figure 22. VHF Input Return Loss (S11) vs. Frequency (High LNA Gain Mode)
Figure 25. VHF In-Band IMD3 vs. Frequency
Figure 26. VHF Out-of-Band IIP3 vs. Frequency Figure 23. VHF Input Return Loss (S11) vs. Frequency (Very Low LNA Gain Mode)
Figure 24. VHF In-Band IIP3 vs. Input Power
Figure 27. VHF Phase Noise vs. Offset Frequency
Rev. PrB | Page 11 of 31
ADMTV803
Preliminary Technical Data
SDA : SWPD `OFF'
I/Q SIGNAL
120
LDO OUTPUT VOLTAGE
Figure 28. Software Power-On Timing
Figure 29. Time-Slicing Power-On Timing
Rev. PrB | Page 12 of 31
Preliminary Technical Data TERMINOLOGY
Input Third-Order Intercept (IIP3) A figure of merit used to determine a component's or system's susceptibility to intermodulation distortion (IMD) from its thirdorder nonlinearities. Two unmodulated carriers at a specified frequency relationship (f1 and f2) are injected into a nonlinear system exhibiting third-order nonlinearities, producing IMD components at (2 x f1) - f2 and (2 x f2) - f1. IIP3 graphically represents the extrapolated intersection of the carrier's input power with the third-order IMD component when plotted in decibels. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa, nfb, where m and n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and
ADMTV803
(fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). Noise Figure (NF) Noise Figure is a measure of how much the SNR degrades as the signal passes through a system.
Noise Figure =
SNRin SNRout
Signal-to-Noise Ratio (SNR) SNR is the ratio of the average signal power to average noise power, excluding harmonics and DC. The value for SNR expresses in decibels. Voltage Standing-Wave Ratio (VSWR) The ratio of the maximum effective voltage to the minimum effective voltage measured along the length of a mismatched radio frequency transmission line.
Rev. PrB | Page 13 of 31
ADMTV803 THEORY OF OPERATION
Preliminary Technical Data
Figure 30. ADMTV803 Interface
LOW NOISE AMPLIFIER (LNA)
ADMTV803 LNA consists of two LNA, and each LNA supports VHF (40~245MHz) band and UHF (470~862MHz) band. The LNA has 4 gain modes, which are 18 dB, 7 dB, -3 dB and -21 dB typically. The LNA gain state can be read from the LNAGAIN register. When LNAGAIN<1:0>=0x3, the gain is in high gain state, LNAGAIN<1:0>=0x2, the gain is in middle gain state, LNAGAIN<1:0>=0x1, the gain is in low gain state, and LNAGAIN<1:0>=0x0, the gain is in very low gain state.
I/Q DOWNCONVERTER
The I/Q downconversion mixer amplifies incoming RF signals from the RFPGA output and converts the signals to baseband.
LOCAL OSCILLATOR
Voltage Controlled Oscillator (VCO)
The ADMTV803 includes an on-chip VCO, which eliminates the need for an external LC tank. This internal VCO uses only 1.8 V and covers the VHF band (54 MHz to 245 MHz) and the UHF band (470 MHz to 862 MHz). Along with the fractional-N PLL, this low phase noise VCO guarantees sufficient performance for mobile reception of worldwide mobile TV.
RF PROGRAMMABLE GAIN AMPLIFIER (PGA)
The RFPGA has a dynamic gain range of 36 dB. RFPGA gain is controlled by digital gain code, which can be read from the RFAGC register. RFAGC register ranges from 0x00 (minimum gain) to 0x5F (maximum gain). The gain step is 0.5 dB.
Phase Locked Loop (PLL)
The PLL synthesizer includes integrated 20-bit fractional-N PLL and integrated loop filter. Integrated loop filter eliminates extra external passive components. In addition to the integrated VCO, the ADMTV803 local oscillator consists of a - fractional-N PLL
Rev. PrB | Page 14 of 31
Preliminary Technical Data
frequency synthesizer. The fractional-N type architecture with a high performance 20-bit - modulator obtains high resolution and fast switching times, as well as good phase noise. To compensate variable VCO gain, control bits of CP_COMP<4:0> are available. Unlike integer-N type synthesizers used in other silicon tuners, - modulated frequency synthesizers provide the following features: * * * Fast switching time. Ultra high frequency resolution. Good phase noise due to its wide bandwidth. *
ADMTV803
(minimum gain) to 0x5F (maximum gain). The RFAGC consists of an LNA and an RFPGA. The RFAGC dynamic range is 75 dB. Baseband gain is determined by the digital gain setting which can be read via the GVBB register.
With these two dynamic ranges (RFAGC = 75 dB and BBAGC = 54 dB), the ADMTV803 dynamic range is larger than 100 dB. For more information about the RFAGC and BBAGC, see the RFAGC Setting and BBAGC Setting sections. The recommended output amplitude of the ADMTV803 is from 300 mV to 700 mV (peak-to-peak voltage at each I/Q output pin). At 500 mV amplitude, the ADMTV803 exhibits its best performance.
Using a 30.4 MHz crystal oscillator with a 20-bit - modulated fractional-N PLL exhibits a very fine frequency resolution of 29 Hz. The PLL can compensate the frequency offset induced by such factors as the frequency error of reference crystal and the temperature drift of a crystal. The local oscillator frequency, fLO, is calculated as the following equations:
RF POWER DETECTOR AND ADJACENT RECEIVED SIGNAL STRENGTH INDICATOR (ADJRSSI)
The take-over point (TOP) divides the operating range of the RFAGC and BBAGC. The BBAGC voltage from the demodulator controls the GVBB. The demodulator generates the BBAGC voltage by measuring I and Q signal level of the tuner output. When the RF input level is getting lower than the TOP, demodulator increases BBPGA gain by increasing BBAGC voltage. When the RF input level is higher than the TOP, the RFPGA operates. As the RF input level increases, RFPGA gain decreases. RF input level of the opposite direction makes RFPGA gain increased. In the middle of the RFPGA operation range, the LNA on/off operation occurs, and this operation expands the dynamic range of the RFAGC block.
f PLL =
f crytal PLLF PLLN + 20 PLLR 2
f LO =
f PLL PLLS
Where: PLLN is the integer divide value selected by the PLLN register. PLLF is the fractional divide value selected by the PLLF register. PLLR is the reference crystal frequency divide ratio selected by PLLR register. PLLS is selected by the VCOLOADBAND<1:0> register value and VCOBAND<1:0> register and frequency range decides VCOLOADBAND<1:0> register value (see the PLL Setting section for more information).
I2C INTERFACE AND CLOCK CONTROL
The ADMTV803 uses the I2C bus interface. The serial data (SDA) and serial clock (SCL) carry information between the devices connected to the bus. Each device is recognized by a unique address and can operate as either a master or slave, depending on the function of the device.
BASEBAND PROGRAMMABLE GAIN LOW-PASS FILTER (LPF) AND AGC
The baseband block contains a programmable gain LPF and output buffer. The 6th order BB LPF's cutoff frequency supports CMMB (UHF band), DTMB, DVB-H, DVB-T, T-DMB, ATSCM/H and ISDB-T (full-seg, 3-seg and 1-seg) modes and 6 dB to 60 dB programmable gain by 0.25 dB step size. To compensate the LPF cutoff frequency variation, the automatic tuning circuit is included. The BB AGC controls the final output amplitude.
POWER-DOWN MODES
The ADMTV803 has two power-down modes.
Software Power-Down
The ADMTV803 has a software power-down mode controlled by the SWPD registers (Address 0x2F, Address 0x30 and Address 0x31).
Time-Slicing Power-Down
The ADMTV803 also supports a time-slicing power-down mode. TSPD controls time-slicing power-down according to register setting (Address 0x31, Address 0x32 and Address 0x33). During time-slicing power down mode, each block can be selected to be on or off according to the register setting.
AUTOMATIC GAIN CONTROL (AGC)
The ADMTV803 LNA has a 4-step gain control with dynamic range of 39 dB. * The RFPGA has a dynamic gain range of 36 dB, and the RFAGC register controls it. The register value is from 0x00
Rev. PrB | Page 15 of 31
ADMTV803 APPLICATIONS INFORMATION
Single(UHF) and Dual(VHF, UHF) Band Application
Preliminary Technical Data
UHF INPUT VDD18 100nF IP 22nH 33nF IN QN
24 23 22 21 20 19
1 VRFIN 2 VS
QP 18 NC 17
QP
VDD18
3 LNALOAD
ADMTV803
BBAGC 16 VDDIO 15 VDD18DIG 14 CLKOUT 13
BBAGC VDDIO VDD18
1nF
4 VDD18RF
470nF VDD18 1nF
5 REGCAP 6
VDD18VCO
CLKOUT
7
8
9
10
11
12
AS TSPD SDA SCL
I/O 1.8 ~ 3.3V 1.8 V GND NC = NO CONNECT
Figure 31. Typical Application Circuit for UHF Single band
UHF INPUT VDD18 100nF IP 22nH 33nF IN QN
24 23 22 21 20 19
IN
VHF INPUT
100nH
1nF
1 VRFIN 2 VS 3 LNALOAD
VDD18BB
URFIN
RSSI
QN
IP
QP 18 NC 17
QP
VDD18 1nF
3.3nH
ADMTV803
BBAGC 16 VDDIO 15 VDD18DIG 14 CLKOUT 13
BBAGC VDDIO VDD18
4 VDD18RF
470nF VDD18 1nF AS
5 REGCAP 6
VDD18VCO XTALO TSPD SDA SCL
CLKOUT
7
8
9
10
11
12
XTALI
AS TSPD SDA SCL
I/O 1.8 ~ 3.3V 1.8 V GND NC = NO CONNECT
Figure 32. Typical Application Circuit for Dual band
Rev. PrB | Page 16 of 31
ANTENNA APPLICATION INFORMATION
I) One antenna solution for VHFH and UHF band
II) One antenna solution for VHFL, VHFH and UHF band
III) Two antennas solution for VHFL, VHFH and UHF band
IV) Two antennas solution for UHF, VHFH and VHFL band Figure 33. Antenna Application Information
Rev. PrB | Page 17 of 31
ADMTV803
RF INPUT STAGE
The ADMTV803 requires RF impedance matching application circuit. The RF impedance matching components should be located as close as possible to the chip(see Figure 36). The VRFIN pin requires 1 nF DC-blocking capacitor to protect the DC coupling. RF impedance matching values can be changed to optimize RF performance. At UHFIN pin, a DC-blocking capacitor is integrated in the IC.
Preliminary Technical Data
VDDIO VDD18
15
VDDIO
VDD18DIG 14 10k 10k CLKOUT 13 CLKIN
DEMODULATOR IC
9 10 11 12
SCL SDA
Figure36. I2C Interface
BBAGC INTERCONNECTIONS
The ADMTV803 supports three AGC modes; analog mode, analog PWM mode and digital PWM mode. Each mode is controlled by demodulator's AGC signal which contains gain control information and it can be connected between demodulator's AGC and ADMTV803's BBAGC without external components (see Figure 39).
Figure 34. RF Input Stage
VCO BIAS/BYPASS CAPACITORS
The ADMTV803 has integrated VCOs/PLLs for LO frequency generation. By using bypass capacitors, these VDD18 power lines should be isolated from noisy power sources. The bypass capacitor of VDD18 power rejects high frequency noise in the power supply. These bypass capacitors should be located as close as possible to chip and GND (see Figure 37).
Figure 37. AGC Connection
Figure 35. VCO Bias/Bypass Capacitors
DIGITAL INTERFACE-- SDA/SCL
The ADMTV803 is controlled by the I2C communication protocol. The serial data (SDA) and serial clock (SCL) carry information between the devices connected with the bus interface. SDA and SCL facilitate bidirectional communication between the ADMTV803 and the master at clock frequency up to 400 kHz. In addition, 10 k pull-up resistors are integrated on chip for the demodulator interface (see Figure38).
Usually demodulator has AGC block which result is expressed as 1-bit PWM type signal. However, some demodulators feed D/A converted analog signal. Most of these feedback signals are accomplished by open-collector or open-drain scheme. ADMTV803 can accompany with any type of demodulator using PCB line connection that just enough by changing its own register setting. In the case of demodulator feedback signal is PWM signal type, the ADMTV803 has pull-up resistor and internal low-pass filtering block to handle PWM feedback signal by direct connection to demodulator. According to demodulator, a PWM signal is various. For these reasons, the ADMTV803 has two PWM signal processing methods, which are digital PWM and analog PWM mode. Thus, the ADMTV803 supports every PWM output signal type of demodulator without external components. 1. Digital PWM mode
Rev. PrB | Page 18 of 31
The ADMTV803 has a digital moving average filter. This filter can find the wanted gain control value of baseband. This mode does not require additional blocks between demodulator and ADMTV803. 1-bit PWM signal can be directly filtered out by tuning averaged data number of digital filter. 2. Analog PWM mode Digital moving average filter only PWM signal processing may suffer from noise issues even though tuning number of averaged data. Therefore, the ADMTV803 also has internal analog lowpass filter for improving wanted baseband gain control value quality. The analog PWM mode employs cascaded analog lowpass filter and digital moving average filter. In this case, internal 8-bit A/D converter is used between analog low-pass filter and digital filter on chip. 3. Analog mode In the other case of demodulator feedback signal is Analog mode (D/A converted analog signal), by using pull-up resistor and analog buffer, the ADMTV803 can find wanted BB gain control value in case of analog type feedback signal processing. This mode does not use digital moving average filter, but analog lowpass filter and A/D converter. The mode changing is accomplished easily by register tuning.
Figure 39. TCXO Application
It is also highly recommended to inquire an optimized oscillator application from TCXO vendors. TCXO output amplitude must be larger than 500 mV p-p. The stability also depends on the demodulator's carrier tracking performance.
Target Frequency (MHz) Load Capacitor (pF) on chip Maximum ESR (ohm) Temperature Stability (ppm) 13 ~ 40 8 TBD 5
It is also noted that default frequency of CLKOUT port at poweron state is the TCXO frequency divided by 1. For example, if the TCXO frequency is 30.4 MHz, then clock output frequency is 30.4 MHz when the chip starts after just power-on state.
REFERENCE CLOCK SELECTION
ADMTV803 supports reference clocks as below. Table 7 shows PLLR register selection. Table 6. PLLR selection according to crystal oscillator
Crystal oscillator 13 MHz to 22 MHz 23 MHz to 40 MHz PLLR<3:0> 0x01 0x02
XIN/XOUT INTERCONNECTIONS
The ADMTV803 supports crystal and temperature-controlled crystal oscillator (TCXO) for a reference clock. When using a crystal, XTALI and XTALO pins are connected to crystal unit. A 1 M feedback resistor and 8 pF load capacitors are integrated on chip. (see Figure 40).
PLL SETTING
As stated in the Local Oscillator section, the ADMTV803 local oscillator (LO) consists of a VCO and a - fractional-N PLL. The ADMTV803 supports a wide range of LO frequencies as shown in Table 7. when using 30.4 MHz reference clock. When changing LO frequencies, users must calculate the PLLN and PLLF register values manually. The Manual PLL Setting Procedure section outlines the steps to adjust these two registers. Table 7. Register Value Selection1
VCOBAND<1:0>: VCO core frequency shift VCOLOADBAND<1:0>: band selection LO Frequency 54 MHz to 57 MHz 58 MHz to 75 MHz 75 MHz to 117MHz 117 MHz to 150MHz 150 MHz to 235 MHz VCOBAND <1:0> 0x3 0x0 0x3 0x0 0x3 VCOLOADBAND <1:0> 0x0 0x0 0x0 0x1 0x1 PLLS (Dec) 8 8 8 4 4 PLLR <3:0> b10 b10 b01 b10 b01
Figure 38. X-TAL Application
It is highly recommended to inquire an optimized oscillator application from crystal vendors. The stability also depends on the demodulator's carrier tracking performance.
Target Frequency (MHz) Load Capacitor (pF) on chip Maximum ESR (ohm) Temperature Stability (ppm) 13 ~ 40 8 TBD 30
In addition, the default setting of CLKOUT port at power-on state is the crystal frequency divided by 1. For example, if the crystal frequency is 30.4 MHz, then clock output frequency is 30.4 MHz when the chip starts after just power-on state. In case of using a temperature-controlled crystal oscillator (TCXO), it should be interfaced to the ADMTV803 via Pin XTALI with a DC block capacitor of 10 nF.
Rev. PrB | Page 19 of 31
ADMTV803
235 MHz to 300 MHz 300 MHz to 470 MHz 470 MHz to 600 MHz 600 MHz to 940 MHz
1
Preliminary Technical Data
0x0 0x3 0x0 0x3 0x2 0x2 0x3 0x3 2 2 1 1 b10 b01 b10 b01
666 PLLN + PLLF = 20 2 30.4
43.81578947 = PLLN +
PLLF 2 20
The PLLN and PLLF values are as follows: PLLN = 21 PLLN = 0x15 PLLF = 0.907894 x 220 = 991995 PLLF = 0xE86BB
The LO frequency is calculated by dividing the PLL frequency by the division ratio according to the PLLS
Manual PLL Setting Procedure
To set the fLO manually, use the following procedure: 1. 2. 3. Reset the tuner. Select the fLO to be oscillated. Select the VCOBAND<1:0> register value and VCOLOADBAND<1:0> register value according to the fLO selection in Table 7. The PLLS value is a division step decided by VCOLOADBAND<1:0> value selection. Use the PLLR value, which has a default of 2 if you use 30.4MHz reference clock. Determine the PLLN and PLLF register values by calculating the following equations:
RFAGC SETTING
The ADMTV803 has dual RF/BB AGC loops. The RF AGC and the BB AGC loops are controlled by demodulator. RF power detector and ADJ RSSI operate automatically to improve linearity for strong signals and interferer injection. RF and baseband PGA block gain can also be set manually for test purposes.
RF Gain Setting (Automatic and Manual Gain Control)
The ADMTV803 RFAGC has two gain control mode, automatic gain control and manual gain control. When RFAGCSEL<1:0> is 0x0, (This is a default setting) RFAGC operates as automatic control mode. For flexibility of RF gain control, the LNA could be controlled independently by changing RFAGCSEL<1:0>. RFAGCSEL <1:0> 0x0 0x1 0x2 0x3 Fully automatic RF gain control Automatic gain control of LNA, Manual control of remained RF blocks Manual control of LNA gain, Automatic gain control of remained RF blocks Fully manual RF gain control Description
4. 5. 6.
f PLL
f crytal PLLF = PLLN + 20 PLLR 2
f LO = f PLL PLLS
where: PLLN is the integer divide value selected by the PLLN register. PLLF is the fractional divide value selected by the PLLF register. PLLR is the reference crystal frequency divide ratio selected by PLLR register. PLLS is selected by the VCOLOADBAND<1:0> register value and VCOBAND<1:0> register and frequency range decides VCOLOADBAND<1:0> register value. Solving these equations give one equation consisting of the PLLN and PLLF variables. PLLN is an integer value, and PLLF is a fractional value multiplied by 220. For example, if the desired fLO = 666 MHz and crystal oscillator frequency = 30.4 MHz. fPLL = 30.4 MHz x PLLN + PLLF 20 2 fLO = 666 MHz =
LNAGAIN_I2C<1:0> and RFAGC_I2C<6:0> could be written LNA gain and RFPGA block gain respectively. These manually set gains will be asserted according to the RFAGC<1:0>.
BB GAIN SETTING
For automatic gain control of BB PGA, the ADMTV803 supports three BBAGC mode, which are digital PWM mode, analog PWM mode and analog mode. Furthermore, the ADMTV803 can set BB PGA gain via manual gain control register setting.
Automatic BB Gain Setting
At initial setting, BB gain(GVBB) is under analog PWM mode. To utilize the BBAGC demodulator feedback signal at this mode, 1. Set GVBBSEL<0> to 0x0
f PLL f = PLL PLLS 1
PLLF 20 2
666 MHz = 30.4 MHz x PLLN +
2. Connect the demodulator feedback of BBAGC to the ADMTV803 directly (Pin 16) Digital PWM mode is enabled by changing BBAGCMODE_SEL<0> as `1'. There is no difference of PCB
Rev. PrB | Page 20 of 31
connection as changing PWM mode from analog PWM to digital PWM mode. The ADMTV803 has internal pull-up resistors to remove external components for demodulator's open-collector or open-drain output. In this case, 1. 2. 3. Set GVBBSEL<0> to 0x0 Set R_BBAGC_PU<2:0> to the desired value. (Refer the I2C map table in detail) Connect the BBAGC of demodulator feedback to the ADMTV803 directly (Pin 16)
1. Set GVBBSEL<0> to 0x1 2. Set GVBB_I2C<7:0> to the desired value (0x00 to 0xD7)
TSPD CONTROL SIGNAL INVERTING
The ADMTV803 time-slicing power-down (TSPD) polarity can be inverted by users demand.
TSPDPOL<0> 0x0 0x1 Status Normal Inverse
On the other hand, analog mode requires different register settings as follows. 1. 2. 3. Set GVBBSEL<0> to 0x0 Set SEL_BBAGCIN_AMODE<0> to 0x1 (Default setting is 0x0) Connect the BBAGC of demodulator feedback to the ADMTV803 directly. (Pin 16)
POWER-DOWN CONTROL
The ADMTV803 has two power-down modes: time-slicing power-down (TSPD pin), and software power-down (SWPD register settings). Recovery time from power-down depends on the PLL lock time and the demodulator's AGC response. * If the TSPD pin is high and a TSPDxxx block register (Address 0x31, Address 0x32 and Address 0x33) is high, the xxx block is powered down. If a SWPDxxx block register is high, the xxx block register (Address 0x2F, Address 0x30 and Address 0x31) is powered down.
Same pull-up resistors, R_BBAGC_PU<2:0> can be set according to the demodulator conditions which are digital and analog PWM mode type.
*
Manual Gain Setting
For manual gain setting, gain control mode must change to manual gain setting. When GVBBSEL<0> set to `1' then BB gain control goes to manual mode. Then, BB gain is controlled by changing GVBB_I2C<7:0>.
In case of time-slicing power-down, all blocks including the crystal oscillator block are powered down. Therefore, all digital parameters are stored as they were before power-down. After being powered on by the TSPD pin, the tuner does not need to operate the VCO searching loop and automatic gain control.
Figure 40. Two Power-Down Modes
Rev. PrB | Page 21 of 31
ADMTV803 I2C OPERATION
Preliminary Technical Data
The ADMTV803 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. The data and clock are fed on the SDA and SCL lines, respectively, as defined by the I2C bus format. The device can either accept data in the write-mode, or send data in the read-mode. The LSB of the address byte sets the device into write-mode if it is low and read mode if it is high.
I2C READ/WRITE ADDRESS
Table 8. I2C Read Address
Address Select Pin (AS) Low High MSB 1 1 1 1 0 0 0 0 0 0 0 1 1 0 LSB 1 1 Address (Hex) 0xC3 0xC5
Table 9. I2C Write Address
Address Select Pin (AS) Low High MSB 1 1 1 1 0 0 0 0 0 0 0 1 1 0 LSB 0 0 Address (Hex) 0xC2 0xC4
I2C BUS FORMAT
Figure 41. I 2C Bus Format
I2C TIMING CHARACTERISTICS
According to standard I2C specification, the clock frequency reaches its maximum 400 kHz in fast-mode and 100 kHz in standard-mode. To communicate with RF tuner, users need to comply with the conditions in this section.
Figure 42. Serial Control Port Read Mode
Rev. PrB | Page 22 of 31
Figure 43. Serial Control Port Write Mode
Serial Control Port Timing
TA = 25C, VDDIO = 2.8 V, GND = 0 V, unless otherwise noted. Table 10. I2C Serial Control Timing
Standard Mode Parameter Hold Time (Repeat) Start Condition SCL Clock Period High Period of the SCL Clock Low Period of the SCL Clock Setup Time for Stop Condition Data Setup Time Data Hold Time for I2C Bus Devices
1 2
Fast Mode Min 0.6 0 0.6 1.3 0.6 1002 03 Max 400 Unit s kHz s s s ns s
Symbol
1
tSHD tCLK tHIGH tLOW tPSU tDSU tDHD
Min 4.0 0 4.0 4.7 4.0 250 03
Max 100
3.454
0.94
After this period, the first clock pulse is generated.
A fast mode I2C bus device can be used in a standard mode I2C bus system, but the tDSU 250ns requirement must then be met. This automatically occurs if the device does not stretch the low period of the SCL signal (tLOW)
3 4
A device must internally provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge of SCL. The maximum tDHD needs to be met only when the device does not stretch the low period of the SCL signal (tLOW)
Figure 44. Serial Control Port Timing
Rev. PrB | Page 23 of 31
ADMTV803
I2C REGISTER MAP
Table 11. Register Listing
Addr (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x07 0x08 0x09 0x12 0x13 0x22 0x23 Type R R R R R R R R R R R R/W R/W Parameter CHIPID CHIPID0 SPLITID RFAGC BBAGC RFAGC /LNA VCO/PLL ADC CTUNE EFUSE EFUSE LNA LNA LNABAND ICONLNA_NORM<3:0> BLANK READEFUSE<7:0> BLANK BLANK BLANK RESERVED RV<5:0> CTUNE<7:0> BLANK (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Preliminary Technical Data
Bit 2
Bit 1
(LSB) Bit 0
CHIPID1<7:0> CHIPID0<7:0> SPLITID<7:0> RFAGC<6:0> GVBB<7:0> CH_FLAG_OUT<1:0> LNAGAIN<1:0> LOCK CTUNE<8> READEFUSE<12:8> RESERVED ICONLNA_SENS<3:0> MODE1: CMMB 8M DVB-T/H, ISDBT FULL SEG, ATSC (TBD) PDVHFM PDVHFL VCOBAND<1:0> PLLN<7:0> PLLF<19:12> PLLF<11:4> PLLF<3:0> BLANK BLANK SWPDLNA SWPD ADJRSSI SWPDCLK DRV TSPDBGR RST_PLL BBAGC MODE_SEL SWPDMIX SWPDADC INIT_VCOC AL POL_BBAG C SWPDBB SWPDBBAG C ANALOG TSPDLNA TSPDADJRS SI TSPDTMPS NS MIXSELBGR RESERVED ADC_BP_ SEL SWPDVCO SWPDDCOS DAC TSPDMIX TSPDADC SWPDLDO SWPD CTUNE TSPDBB TSPDBBAGC ANALOG TSPDCLK DRV MIXGAIN BOOST SEL_BBAGC IN_AMODE PLLR<3:0> R_BBAGC_PU<2:0> AVGCNT_SET<3:0> SWPDPLL SWPDRTUNE SWPDBGR SWPD TMPSNS TSPDLDO TSPDC TUNE SWPDPDE T SWPDDIG MODE2: CMMB 2M MODE3: T-DMB, ISDB-T 1SEG ISDB-T 3SEG RESERVED PLLN<9:8>
0x24
R/W
LNA/LPF
ICONLNA_ACR<3:0>
RESERVED
0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2E 0x2F 0x30
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
LNA/LPF VCO/PLL PLL PLL PLL PLL PLL/BBAGC BBAGC SWPD SWPD SWPD/TSP D TSPD TSPD/DIVID ER CLOCK OUTPUT MIXER/LNA MIXER/PWR . DETECTOR LPF LPF RFAGC/VCO TSPD/VCO RESERVED
PDDIV3
PDUHF
PDVHFH
VCOLOADBAND<1:0>
RESERVED
0x31 0x32
R/W R/W
SWPDOSC TSPDPDET
TSPDVCO TSPDDCOS DAC TSPDOSC
TSPDPLL TSPDRTU NE
0x33
R/W
BLANK
TSPDDIG
DIVCLKDRV<1:0>
0x3C 0x3D 0x3E 0x4B 0x4D 0x4E 0x59
R/W R/W R/W R/W R/W R/W R/W
BLANK CALPWD BLANK DETENA TSPDPOL ENRTUNE
RESERVED RESERVED
RESERVED MIXCTUNE<3:0>
RESERVED RESERVED RESERVED
STG2_Q_CAL<2:0> BQC<7:0> ADJENA PDPTATDIV RESERVED
Rev. PrB | Page 24 of 31
STG3_Q_CAL<2:0> RESERVED RESERVED
Addr (Hex) 0x5D 0x7F 0x80 0x88 0x89 0x8B 0x93
NOTES
Type R/W R/W R/W R/W R/W R/W R/W
Parameter BBAGC LNA RFAGC BBAGC RFAGC PWR. DETECTOR MIXER
(MSB) Bit 7 GVBBSEL
Bit 6
Bit 5
Bit 4
Bit 3 RESERVED
Bit 2 RESERVED RESERVED
Bit 1
(LSB) Bit 0
LNAGAIN_I2C<1:0> RFAGCSEL<1:0> IGCAL<3:0> BLANK BLANK RESERVED RFAGC_I2C<6:0>
QGCAL<3:0>
PWD_DCOSDAC<5:0> MIXICAL<1:0> MIXQCAL<1:0>
The RESERVED bits are not supposed to be changed. R: Read only. R/W: Read and Write.
REGISTER DESCRIPTIONS
Table 12. Read Only Register
Address (Hex) 0x00 0x01 0x02 0x03 0x04 Bit(s) <7:0> <7:0> <7:0> <6:0> <7:0> Name CHIPID1<7:0> CHIPID0<7:0> SPLITID<7:0> RFAGC<6:0> GVBB<7:0> Description Chip ID. Chip ID. Chip split ID. RFAGC gain state value. BBAGC gain control (0.25dB Step). <7:0> = 0x00: minimum gain. <7:0> = 0xD7: maximum gain. Channel state flag output. <1:0> = 0x0: normal state. <1:0> = 0x1: sensitivity state. <1:0> = 0x2: ACR state. LNA gain state. <1:0> = 0x0: very low gain. <1:0> = 0x1: low gain. <1:0> = 0x2: middle gain. <1:0> = 0x3: high gain. PLL lock indicator. <0> = 0x0: PLL is unlocked. <0> = 0x1: PLL is locked. Internal RTUNE setting value. Calculated C TUNE setting value. Calculated C TUNE setting value. Read Fuse programming data in READ mode Read Fuse programming data in READ mode
0x05
<3:2>
CH_FLAG_OUT<1:0>
<1:0>
LNAGAIN<1:0>
0x07
<0>
LOCK<0>
0x08 0x09 0x12 0x13
<6:1> <0> <7:0> <4:0> <7:0>
RV<5:0> CTUNE<8> CTUNE<7:0> READEFUSE<12:8> READEFUSE<7:0>
Table 13. Read/Write Register
Address (Hex) 0x22 Bit(s) Name <7> LNABAND<0> Description LNA/MIXER LNA band selection. <0> = 0x0: VHF <0> = 0x1: UHF Mixer Bias current selection. <0> = 0x0: PTAT current <0> = 0x1: BGR current
Rev. PrB | Page 25 of 31
0x3C
<6>
MIXSELBGR<0>
ADMTV803
<3> MIXGAINBOOST<0>
Preliminary Technical Data
Mixer Gain manual control. <0> = 0x0: default <0> = 0x1: 6dB gain increase Mixer trans-impedance amplifier 1st order low pass filter capacitor tuning control. <3:0> = 0x0: BW maximum <3:0> = 0xF: BW minimum Mixer's phase calibration <1:0> = 0x0: 0 degree <1:0> = 0x3: -3 degree Mixer's phase calibration <1:0> = 0x0: 0 degree <1:0> = 0x3: +3 degree BASEBAND LPF cutoff frequency selection. <0> = 0x1: Mode1 (MODE2<0> and MODE3<0> = 0x0). LPF cutoff frequency selection. <0> = 0x1: MODE2 (MODE1<0> and MODE3<0> = 0x0). LPF cutoff frequency selection <0> = 0x1: MODE3 (MODE1<0> and MODE2<0>= 0x0). Biquad LPF 2nd stage Q control. Biquad LPF 3rd stage Q control. Cap. bank value after Fc tuning. This value can be changed by Fc tuning VCO/PLL Power down div3 path. Power down UHF path. Power down VHF high path. Power down VHF middle path. Power down VHF low path. Select of band. <1:0> = 0x0 : VHFL <1:0> = 0x1 : VHFM <1:0> = 0x2 : VHFH <1:0> = 0x3 : UHF VCO core frequency range selection (manual control. <1:0>= 0x0: low freq <1:0>= 0x3: high freq PLL feedback divider integer words. PLL feedback divider integer words. PLL feedback divider fractional words. PLL feedback divider fractional words. PLL feedback divider fractional words. PLL reference divider integer value. PLL reset. <0>= 0x1: Reset <0>= 0x0 : Release Initial VCO search loop start reset signal. <0>= 0x0 ->0x1 RF POWER DETECTOR Power Detector DC Offset Calibration mode. <0> = 0x0: stop calibration <0>= 0x1: calibration 6-bit input of Power Detector DC offset Calibration DAC.
Rev. PrB | Page 26 of 31
0x3D
<3:0>
MIXCTUNE<3:0>
0x93
<1:0>
MIXQCAL<1:0>
<3:2>
MIXICAL<3:2>
0x24
<3>
<2> <1>
MODE1<0>: CMMB 8M DVB-T/H, ISDB-T FULL SEG, ATSC-M/H MODE2<0> : CMMB 2M MODE3<0> : T-DMB, ISDB-T 1SEG, ISDB-T 3SEG STG2_Q_CAL<2:0> STG3_Q_CAL<2:0> BQC<7:0> PDDIV3<0> PDUHF<0> PDVHFH<0> PDVHFM<0> PDVHFL<0> VCOLOADBAND<1:0>
0x3E 0x4B 0x25
<5:3> <2:0> <7:0> <7> <6> <5> <4> <3> <7:6>
0x26
<3:2>
VCOBAND<1:0>
0x27 0x28 0x29 0x2A 0x2B
<1:0> <7:0> <7:0> <7:0> <7:4> <3:0> <6>
PLLN<9:8> PLLN<7:0> PLLF<19:12> PLLF<11:4> PLLF<3:0> PLLR<3:0> RST_PLL<0>
<5>
INIT_VCOCAL<0>
0x3D
<7>
CALPWD<0>
0x8B
<5:0>
PWD_DCOSDAC<5:0>
0x2B
<3>
SEL_BBAGCIN_AMODE<0 >
<2:0> R_BBAGC_PU<2:0>
0x2E
<6>
BBAGCMODE_SEL<0>
<5>
POL_BBAGC<0>
<4>
ADC_BP_SEL<0>
<3:0> 0x5D <7>
AVGCNT_SET<3:0> GVBBSEL<0>
0x87 0X88
<7:0> <3:0> <7:4> <5:0> <4>
GVBB_I2C<7:0> QGCAL<3:0> IGCAL<3:0> RVI2C<5:0> READEN
0x80 0x2B
BBAGC INTERFACE AGC input selection mode at ADC mode. <0>= 0x0 : PWM signal is connected to analog AGC LPF <0>= 0x1 : analog signal which is buffered by analog buffer is connected to analog AGC LPF. Pull up resistor value control. <2:0> = 0x0 : open <2:0> = 0x1 : 10 k Ohm <2:0> = 0x2 : 7.07 k Ohm <2:0> = 0x3 : 5 k Ohm <2:0> = 0x4 : 3.5 k Ohm <2:0> = 0x5 : 2.5 k Ohm <2:0> = 0x6 : 1.77 k Ohm <2:0> = 0x7 : 1.25 k Ohm BBAGC Selection bit to determine the BBAGC mode. <0>=0x0: ADC mode <0>=0x1: PWM mode Polarity inverting bit of PWM input signal. <0>=0x0: Proportional PWM signal duty cycle. <0>=0x1: Inverse proportional PWM signal duty cycle Selection bit. <0>=0x0: Average filter output <0>= 0x1: Bypassing ADC input when '1' asserted. To set the averaging date number of BBAGC average filter (Maximum value = 0xA) Number of averaged data = 2^(AVGCNT_SET + 1 + 8 * BBAGCMODE_SEL) GVBB decoder selection bit. <0>=0x0: GVBB decoded output <0>=0x1: GVBB_I2C value Manual setting value for GVBB BB Q path gain calibration value BB I path gain calibration value RTUNE External rtune code input. if extrtune is high, RVI2C is bypassed to RV EFUSE After chip reset, READEN should go to high (>10us) and then fall to low to make READEFUSE data valid RF AGC Data enable bit to using A-to-D converted of RF power detector data for RFAGC internal calculation. Data enable bit from ADJ RSSI. Manual control LNA gain value. Selection bit. <1:0>=0x0: Calculated LNA gain code, Calculated RFAGC value <1:0>=0x1: Calculated LNA gain code, Manually asserted RFAGC value <1:0>=0x2: Manually asserted LNA gain code, Calculated RFAGC value <1:0>=0x3: Manually asserted LNA gain code, Manually asserted RFAGC value AGC counter step at saturation mode = 2^(SATSTEP) Manual control RFAGC value. CLOCK OUTPUT DRIVER Divider for clock output driver. <1:0>=0x0: Output = master clock <1:0>=0x1: Output = master clock / 2 <1:0>=0x2: Output = master clock / 4 SOFTWARE POWER DOWN Software power down of LNA.
Rev. PrB | Page 27 of 31
0x4D
<7> <3> <7:6> <7:6>
DETENA<0> ADJENA<0> LNAGAIN_I2C<1:0> RFAGCSEL<1:0>
0x7F 0x80
0x82 0x89 0x33
<5:3> <6:0> <1:0>
SATSTEP<2:0> RFAGC_I2C<6:0> DIVCLKDRV<1:0>
0x2F
<7>
SWPDLNA<0>
ADMTV803
Preliminary Technical Data
<0>=0x0: power on <0>=0x1: power down Software power down of mixer. <0>=0x0: power on <0>=0x1: power down Software power down of baseband. <0>=0x0: power on <0>=0x1: power down Software power down of VCO. <0>=0x0: power on <0>=0x1: power down Software power down of LDO. <0>=0x0: power on <0>=0x1: power down Software power down of PLL. <0>=0x0: power on <0>=0x1: power down Software power down of BGR. <0>=0x0: power on <0>=0x1: power down Software power down of RF power detector. <0>=0x0: power on <0>=0x1: power down Software power down of ADJRSSI. <0>=0x0: power on <0>=0x1: power down Software power down of ADC. <0>=0x0: power on <0>=0x1: power down Software power down of BBAGC analog part. <0>=0x0: power on <0>=0x1: power down Software power down of DC offset DAC. <0>=0x0: power on <0>=0x1: power down Software power down of CTUNE. <0>=0x0: power on <0>=0x1: power down Software power down of RTUNE. <0>=0x0: power on <0>=0x1: power down Software power down of temperature sensor. <0>=0x0: power on <0>=0x1: power down Software power down of digital (clock gating). <0>=0x0: power on <0>=0x1: power down Software power down of clock driver. <0>=0x0: power on <0>=0x1: power down Software power down of crystal oscillator. <0>=0x0: power on <0>=0x1: power down TIME-SLICING POWER DOWN Time-slicing power down of LNA.
Rev. PrB | Page 28 of 31
<6>
SWPDMIX<0>
<5>
SWPDBB<0>
<4>
SWPDVCO<0>
<3>
SWPDLDO<0>
<2>
SWPDPLL<0>
<1>
SWPDBGR<0>
<0>
SWPDPDET<0>
0x30
<7>
SWPDADJRSSI<0>
<6>
SWPDADC<0>
<5>
SWPDBBAGCANALOG<0>
<4>
SWPDDCOSDAC<0>
<3>
SWPDCTUNE<0>
<2>
SWPDRTUNE<0>
<1>
SWPDTMPSNS<0>
<0>
SWPDDIG<0>
0x31
<7>
SWPDCLKDRV
<6>
SWPDOSC
0x31
<5>
TSPDLNA <0>
<4>
TSPDMIX<0>
<3>
TSPDBB<0>
<2>
TSPDVCO<0>
<1>
TSPDLDO<0>
<0>
TSPDPLL<0>
0x32
<7>
TSPDBGR<0>
<6>
TSPDPDET<0>
<5>
TSPDADJRSSI<0>
<4>
TSPDADC<0>
<3>
TSPDBBAGCANALOG<0>
<2>
TSPDDCOSDAC<0>
<1>
TSPDCTUNE<0>
<0>
TSPDRTUNE<0>
0x33
<5>
TSPDTMPSNS<0>
<4>
TSPDDIG<0>
<3>
TSPDCLKDRV<0>
<2>
TSPDOSC<0>
0x4E
<7>
TSPDPOL
<0>=0x0: power on <0>=0x1: power down Time-slicing power down of mixer. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of baseband. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of VCO. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of LDO. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of PLL. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of BGR. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of RF power detector. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of ADJRSSI. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of ADC. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of BBAGC analog part. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of DC offset DAC. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of CTUNE. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of RTUNE. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of temperature sensor. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of digital (clock gating). <0>=0x0: power on <0>=0x1: power down Time-slicing power down of clock driver. <0>=0x0: power on <0>=0x1: power down Time-slicing power down of crystal oscillator. <0>=0x0: power on <0>=0x1: power down TSPD polarity change. <0>=0x0: normal <0>=0x1: inverse
NOTES Rev. PrB | Page 29 of 31
ADMTV803
R: Read only. R/W: Read and Write.
Preliminary Technical Data
Rev. PrB | Page 30 of 31
OUTLINE DIMENSIONS
Figure 45. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x4 mm Body Dimensions shown in millimeters
ORDERING GUIDE
Model ADMTV803ACPZRL 1 ADMTV803BCPZRL1 ADMTV803A-EBZ1 ADMTV803B-EBZ1
1
Band UHF UHF, VHF UHF UHF, VHF
Temperature Range -40C to + 85C -40C to + 85C
Package Description 24-Lead Frame Chip Scale Package [LFCSP] 24-Lead Frame Chip Scale Package [LFCSP] Evaluation Board Evaluation Board
Package Option CP-24-4 CP-24-4
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07909-0-4/09(PrB)
Rev. PrB | Page 31 of 31

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